/*
 * Copyright (c) 2022-2023 Termony Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice, this list of
 *    conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
 *    of conditions and the following disclaimer in the documentation and/or other materials
 *    provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
 *    to endorse or promote products derived from this software without specific prior written
 *    permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include "los_arch_gic.h"
#include "los_arch_cpu.h"
#include "los_interrupt.h"
#include "los_debug.h"

#if (LOSCFG_PLATFORM_GIC_VERSION == 1) || (LOSCFG_PLATFORM_GIC_VERSION == 2)

static struct {
    UINT16 maxIrq; /* The maximum number of interrupts supported by the processor. */
    UINT16 priOft; /* Implemented priority bit offset. */
    struct {
    UINT32 offset; /* the first interrupt index in the vector table */
    UINT64 distBase; /* the base address of the gic distributor */
    UINT64 cpuBase; /* the base address of the gic cpu interface */
    } gic[LOSCFG_PLATFORM_GIC_NUMBER];
} g_gicCb;

/** Macro to access the Generic Interrupt Controller Distributor (GICD) */
#define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000U)
#define GIC_DIST_TYPE(hw_base)              __REG32((hw_base) + 0x004U)
#define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080U + ((n)/32U) * 4U)
#define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100U + ((n)/32U) * 4U)
#define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180U + ((n)/32U) * 4U)
#define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200U + ((n)/32U) * 4U)
#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280U + ((n)/32U) * 4U)
#define GIC_DIST_ACTIVE_SET(hw_base, n)     __REG32((hw_base) + 0x300U + ((n)/32U) * 4U)
#define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x380U + ((n)/32U) * 4U)
#define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400U +  ((n)/4U) * 4U)
#define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800U +  ((n)/4U) * 4U)
#define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U)
#define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00U)
#define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U)
#define GIC_DIST_SPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U)
#define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8U)

/** Macro to access the Generic Interrupt Controller Interface (GICC) */
#define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00U)
#define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04U)
#define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08U)
#define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0cU)
#define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10U)
#define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14U)
#define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18U)
#define GIC_CPU_IIDR(hw_base)               __REG32((hw_base) + 0xFCU)


UINT32 HalGicGetActiveIrq(UINT32 gic)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);

    UINT32 irqId = GIC_CPU_INTACK(g_gicCb.gic[gic].cpuBase);
    return irqId + g_gicCb.gic[gic].offset;
}

VOID HalGicIrqAck(UINT32 gic, UINT32 irqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    irqId = irqId - g_gicCb.gic[gic].offset;
    GIC_DIST_PENDING_CLEAR(g_gicCb.gic[gic].distBase, irqId) = 1UL << (irqId % 32);
    GIC_CPU_EOI(g_gicCb.gic[gic].cpuBase) = irqId;
}


VOID HalGicIrqMask(UINT32 gic, UINT32 irqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    irqId = irqId - g_gicCb.gic[gic].offset;
    GIC_DIST_ENABLE_CLEAR(g_gicCb.gic[gic].distBase, irqId) = 1UL << (irqId % 32);
    __DSB();
    __ISB();
    __DMB();
}

VOID HalGicIrqUmask(UINT32 gic, UINT32 irqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    irqId = irqId - g_gicCb.gic[gic].offset;
    GIC_DIST_ENABLE_SET(g_gicCb.gic[gic].distBase, irqId) = 1UL << (irqId % 32);
    __DSB();
    __ISB();
    __DMB();
}


VOID HalGicBroadcastSgi(UINT32 gic, UINT32 irqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    irqId = irqId - g_gicCb.gic[gic].offset;
    GIC_DIST_SOFTINT(g_gicCb.gic[gic].distBase) = \
        (1 << 24) | (1 << 15) | (irqId & 0xF);
    __DSB();
    __ISB();
}

VOID HalGicSinglecastSgi(UINT32 gic, UINT32 irqId, UINT32 cpuId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    UINT32 targetList = (1 << cpuId);
    irqId = irqId - g_gicCb.gic[gic].offset;
    GIC_DIST_SOFTINT(g_gicCb.gic[gic].distBase) = \
        (3 << 24) | ((targetList & 0xFF) << 16) | (1 << 15) | (irqId & 0xF);
    __DSB();
    __ISB();
}

VOID HalGicMulticastSgi(UINT32 gic, UINT32 irqId, UINT32 targetList)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    irqId = irqId - g_gicCb.gic[gic].offset;
    GIC_DIST_SOFTINT(g_gicCb.gic[gic].distBase) = \
        (3 << 24) | ((targetList & 0xFF) << 16) | (1 << 15) | (irqId & 0x0F);
    __DSB();
    __ISB();
}


VOID HalGicSetPendingIrq(UINT32 gic, UINT32 irqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    irqId = irqId - g_gicCb.gic[gic].offset;
    if (irqId >= 16) {
        GIC_DIST_PENDING_SET(g_gicCb.gic[gic].distBase, irqId) = 1UL << (irqId % 32);
    } else {
        GIC_DIST_SPENDSGI(g_gicCb.gic[gic].distBase, irqId) = 1UL << ((irqId % 4) * 8);
    }
    __DSB();
    __ISB();
    __DMB();
}

UINT32 HalGicGetPendingIrq(UINT32 gic, UINT32 irqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    UINT64 pending;
    irqId = irqId - g_gicCb.gic[gic].offset;
    if (irqId >= 16) {
        pending = (GIC_DIST_PENDING_SET(g_gicCb.gic[gic].distBase, irqId) >> (irqId % 32)) & 1UL;
    } else {
        pending = (GIC_DIST_SPENDSGI(g_gicCb.gic[gic].distBase, irqId) >> ((irqId % 4) * 8)) & 0xFFUL;
    }

    return (pending != 0) ? 1 : 0;
}

VOID HalGicClearPendingIrq(UINT32 gic, UINT32 irqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    irqId = irqId - g_gicCb.gic[gic].offset;
    if (irqId >= 16) {
        GIC_DIST_PENDING_CLEAR(g_gicCb.gic[gic].distBase, irqId) = 1U << (irqId % 32U);
    } else {
        GIC_DIST_CPENDSGI(g_gicCb.gic[gic].distBase, irqId) = 1U << ((irqId % 4U) * 8U);
    }
    __DSB();
    __ISB();
    __DMB();
}


VOID HalGicSetIrqConfig(UINT32 gic, UINT32 irqId, UINT32 config)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    irqId = irqId - g_gicCb.gic[gic].offset;
    UINT64 icfgr = GIC_DIST_CONFIG(g_gicCb.gic[gic].distBase, irqId);
    UINT64 shift = (irqId % 16U) << 1U;

    icfgr &= (~(3U << shift));
    icfgr |= (config << shift);
    GIC_DIST_CONFIG(g_gicCb.gic[gic].distBase, irqId) = icfgr;
}

UINT32 HalGicIrqGetConfig(UINT32 gic, UINT32 irqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    irqId = irqId - g_gicCb.gic[gic].offset;
    return (GIC_DIST_CONFIG(g_gicCb.gic[gic].distBase, irqId) >> ((irqId % 16U) >> 1U));
}


VOID HalGicIrqSetTargetCpu(UINT32 gic, UINT32 irqId, UINT32 cpuMask)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    irqId = irqId - g_gicCb.gic[gic].offset;
    UINT64 target = GIC_DIST_TARGET(g_gicCb.gic[gic].distBase, irqId);

    target &= ~(0x0FFUL << ((irqId % 4U)*8U));
    target |= cpuMask << ((irqId % 4U)*8U);
    GIC_DIST_TARGET(g_gicCb.gic[gic].distBase, irqId) = target;
}

UINT32 HalGicIrqGetTargetCpu(UINT32 gic, UINT32 irqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    irqId = irqId - g_gicCb.gic[gic].offset;
    return (GIC_DIST_TARGET(g_gicCb.gic[gic].distBase, irqId) >> ((irqId % 4U) * 8U)) & 0xFFUL;
}


VOID HalGicSetIrqPriority(UINT32 gic, UINT32 irqId, UINT8 priority)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);
    LOS_ASSERT(priority < (1 << g_gicCb.priOft));

    UINT32 mask;
    irqId = irqId - g_gicCb.gic[gic].offset;
    priority = priority << g_gicCb.priOft;
    mask = GIC_DIST_PRI(g_gicCb.gic[gic].distBase, irqId);
    mask &= ~(0xFFUL << ((irqId % 4) * 8));
    mask |= ((UINT32) priority << ((irqId % 4) * 8));
    GIC_DIST_PRI(g_gicCb.gic[gic].distBase, irqId) = mask;
}

UINT8 HalGicGetIrqPriority(UINT32 gic, UINT32 irqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    UINT32 mask;
    irqId = irqId - g_gicCb.gic[gic].offset;
    mask = GIC_DIST_PRI(g_gicCb.gic[gic].distBase, irqId);
    return (UINT8) (((mask >> ((irqId % 4) * 8)) & 0xff) >> g_gicCb.priOft);
}


VOID HalGicSetInterfacePriorityMask(UINT32 gic, UINT8 priority)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(priority < (1 << g_gicCb.priOft));

    GIC_CPU_PRIMASK(g_gicCb.gic[gic].cpuBase) = ((UINT32) priority << g_gicCb.priOft);
}

UINT8 HalGicGetInterfacePriorityMask(UINT32 gic)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);

    return (UINT8) ((GIC_CPU_PRIMASK(g_gicCb.gic[gic].cpuBase) & 0xFF) >> g_gicCb.priOft);
}


VOID HalGicSetBinaryPoint(UINT32 gic, UINT32 binaryPoint)
{
    GIC_CPU_BINPOINT(g_gicCb.gic[gic].cpuBase) = binaryPoint & 0x7UL;
}

UINT32 HalGicGetBinaryPoint(UINT32 gic)
{
    return GIC_CPU_BINPOINT(g_gicCb.gic[gic].cpuBase) & 0x7UL;
}


VOID HalGicSetGroup(UINT32 gic, UINT32 irqId, UINT32 group)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(group <= 1U);

    irqId = irqId - g_gicCb.gic[gic].offset;
    UINT32 igroupr = GIC_DIST_IGROUP(g_gicCb.gic[gic].distBase, irqId);
    UINT32 shift = (irqId % 32U);

    igroupr &= (~(1U << shift));
    igroupr |= ((group & 0x1U) << shift);
    GIC_DIST_IGROUP(g_gicCb.gic[gic].distBase, irqId) = igroupr;
}

UINT32 HalGicGetGroup(UINT32 gic, UINT32 irqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    irqId = irqId - g_gicCb.gic[gic].offset;
    return (GIC_DIST_IGROUP(g_gicCb.gic[gic].distBase, irqId) >> (irqId % 32U)) & 0x1UL;
}


UINT32 HalGicGetIrqStatus(UINT32 gic, UINT32 irqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);

    irqId = irqId - g_gicCb.gic[gic].offset;
    UINT32 active = (GIC_DIST_ACTIVE_SET(g_gicCb.gic[gic].distBase, irqId) >> (irqId % 32U)) & 0x1UL;
    UINT32 pending = (GIC_DIST_PENDING_SET(g_gicCb.gic[gic].distBase, irqId) >> (irqId % 32U)) & 0x1UL;
    return (active << 1U) | pending;
}

VOID HalGicClearActiveIrq(UINT32 gic, UINT32 irqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);
    LOS_ASSERT(irqId < LOSCFG_PLATFORM_HWI_LIMIT);

    irqId = irqId - g_gicCb.gic[gic].offset;
    GIC_DIST_ACTIVE_CLEAR(g_gicCb.gic[gic].distBase, irqId) = 1U << (irqId % 32U);
}


UINT32 HalGicGetHighPendingIrq(UINT32 gic)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);

    return GIC_CPU_HIGHPRI(g_gicCb.gic[gic].cpuBase);
}


UINT32 HalGicGetInterfaceId(UINT32 gic)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);

    return GIC_CPU_IIDR(g_gicCb.gic[gic].cpuBase);
}


UINT32 HalGicGetMaxIrqNum(VOID)
{
    return g_gicCb.maxIrq;
}


STATIC VOID HalGicDistributorInit(UINT32 gic, UINT32 distributorBase, UINT32 startIrqId)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);

    g_gicCb.gic[gic].distBase = (UINT64) distributorBase;
    g_gicCb.gic[gic].offset = startIrqId;

    /* 获取支持的中断个数. */
    UINT32 gicType = GIC_DIST_TYPE(g_gicCb.gic[gic].distBase);
    g_gicCb.maxIrq = (UINT16) (((gicType & 0x1f) + 1) * 32);

    /* 获取实现的优先级位数. */
    GIC_DIST_PRI(g_gicCb.gic[gic].distBase, 32) = 0xff000000UL;
    g_gicCb.priOft = CLZ(~ GIC_DIST_PRI(g_gicCb.gic[gic].distBase, 32));

    /*
     * The GIC only supports up to 1020 interrupt sources.
     * Limit this to either the architected maximum, or the
     * platform maximum.
     */
    if (g_gicCb.maxIrq > 1020) {
        g_gicCb.maxIrq = 1020;
    }
    /* the platform maximum interrupts */
    if (g_gicCb.maxIrq > LOSCFG_PLATFORM_HWI_LIMIT) {
        g_gicCb.maxIrq = LOSCFG_PLATFORM_HWI_LIMIT;
    }

    UINT64 cpumask = 1U << 0U;
#ifdef ARM_SPI_BIND_CPU_ID
    cpumask = 1U << ARM_SPI_BIND_CPU_ID;
#endif
    cpumask |= cpumask << 8U;
    cpumask |= cpumask << 16U;
    cpumask |= cpumask << 24U;

    GIC_DIST_CTRL(g_gicCb.gic[gic].distBase) = 0x0U;
    /* Set all global interrupts to be level triggered, active low. */
    for (UINT32 i = 32U; i < g_gicCb.maxIrq; i += 16U) {
        GIC_DIST_CONFIG(g_gicCb.gic[gic].distBase, i) = 0x0U;
    }
    /* Set all global interrupts to this CPU only. */
    for (UINT32 i = 32U; i < g_gicCb.maxIrq; i += 4U) {
        GIC_DIST_TARGET(g_gicCb.gic[gic].distBase, i) = cpumask;
    }

    /* Set priority on all interrupts. */
    for (UINT32 i = 0U; i < g_gicCb.maxIrq; i += 4U) {
        GIC_DIST_PRI(g_gicCb.gic[gic].distBase, i) = 0xa0a0a0a0U;
    }
    /* Disable all interrupts. */
    for (UINT32 i = 0U; i < g_gicCb.maxIrq; i += 32U) {
        GIC_DIST_ENABLE_CLEAR(g_gicCb.gic[gic].distBase, i) = 0xffffffffU;
    }
    /* All interrupts defaults to IGROUP1(IRQ). */
    for (UINT32 i = 0U; i < g_gicCb.maxIrq; i += 32U) {
        GIC_DIST_IGROUP(g_gicCb.gic[gic].distBase, i) = 0U;
    }
    /* Enable group0 and group1 interrupt forwarding. */
    GIC_DIST_CTRL(g_gicCb.gic[gic].distBase) = 0x01U;
}

STATIC VOID HalGicCpuInterfaceInit(UINT32 gic, UINT32 cpuInterfaceBase)
{
    LOS_ASSERT(gic < LOSCFG_PLATFORM_GIC_NUMBER);

    g_gicCb.gic[gic].cpuBase = (UINT64) cpuInterfaceBase;

    GIC_CPU_PRIMASK(g_gicCb.gic[gic].cpuBase) = 0xf0U;
    GIC_CPU_BINPOINT(g_gicCb.gic[gic].cpuBase) = 0x7U;
    /* Enable CPU interrupt */
    GIC_CPU_CTRL(g_gicCb.gic[gic].cpuBase) = 0x01U;
}

VOID HalGicInit(UINT32 gic, UINT32 startIrqId)
{
    STATIC BOOL gicInitFlag = FALSE;
    if (gicInitFlag == TRUE) {
        return;
    }

    HalGicDistributorInit(gic, LOSCFG_PLATFORM_GIC_DIST_BASE_ADDR, startIrqId);
    HalGicCpuInterfaceInit(gic, LOSCFG_PLATFORM_GIC_CPU_BASE_ADDR);
    gicInitFlag = TRUE;
}


VOID HalGicDumpType(UINT32 gic)
{
    UINT32 gic_type = GIC_DIST_TYPE(g_gicCb.gic[gic].distBase);
    PRINTK("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
           (GIC_DIST_ICPIDR2(g_gicCb.gic[gic].distBase) >> 4U) & 0xfUL,
           g_gicCb.gic[gic].distBase,
           g_gicCb.maxIrq,
           gic_type & (1U << 10U) ? "has" : "no",
           gic_type);
}

VOID HalGicDump(UINT32 gic)
{
    UINT32 k = GIC_CPU_HIGHPRI(g_gicCb.gic[gic].cpuBase);
    PRINTK("--- high pending priority: %d(%08x)\n", k, k);

    PRINTK("--- hw mask ---\n");
    for (UINT32 i = 0U; i < g_gicCb.maxIrq / 32U; i++) {
        PRINTK("0x%08x, ", GIC_DIST_ENABLE_SET(g_gicCb.gic[gic].distBase, i * 32U));
    }

    PRINTK("\n--- hw pending ---\n");
    for (UINT32 i = 0U; i < g_gicCb.maxIrq / 32U; i++) {
        PRINTK("0x%08x, ", GIC_DIST_PENDING_SET(g_gicCb.gic[gic].distBase, i * 32U));
    }

    PRINTK("\n--- hw active ---\n");
    for (UINT32 i = 0U; i < g_gicCb.maxIrq / 32U; i++) {
        PRINTK("0x%08x, ", GIC_DIST_ACTIVE_SET(g_gicCb.gic[gic].distBase, i * 32U));
    }
    PRINTK("\n");
}

#endif /* LOSCFG_PLATFORM_GIC_VERSION */
